• "Ola Fosheim =?UTF-8?B?R3LDuHN0YWQi?= (9/9) Feb 09 2015 ldc.gccbuiltins_x86.di does not contain:
• David Nadlinger (8/17) Feb 09 2015 Unfortunately, LLVM only offers intrinsics for operations that
• "Ola Fosheim =?UTF-8?B?R3LDuHN0YWQi?= (4/20) Feb 09 2015 Thanks, I found a "role model" here:

"Ola Fosheim =?UTF-8?B?R3LDuHN0YWQi?= writes:

ldc.gccbuiltins_x86.di does not contain:

__m256 _mm256_add_ps (__m256 a, __m256 b)
#include "immintrin.h"
Instruction: vaddps ymm, ymm, ymm
CPUID Flags: AVX

But it does contain less important instructions such a 256bit 
"addsub".

I am trying to build up a set of standard Intel intrinsics, but 
not sure how to work around this (or did I miss something?)

"David Nadlinger" <code klickverbot.at> writes:

On Monday, 9 February 2015 at 09:43:26 UTC, Ola Fosheim Grøstad 
wrote:
 ldc.gccbuiltins_x86.di does not contain:

 __m256 _mm256_add_ps (__m256 a, __m256 b)
 #include "immintrin.h"
 Instruction: vaddps ymm, ymm, ymm
 CPUID Flags: AVX

 But it does contain less important instructions such a 256bit 
 "addsub".

 I am trying to build up a set of standard Intel intrinsics, but 
 not sure how to work around this (or did I miss something?)

Unfortunately, LLVM only offers intrinsics for operations that 
are not expressible in standard LLVM IR.

Just using the addition operator on the appropriate vector types 
with AVX enabled might already yield the result you are looking 
for. Otherwise, you can use inline IR (see e.g. ldc.simd).

David

"Ola Fosheim =?UTF-8?B?R3LDuHN0YWQi?= writes:

On Monday, 9 February 2015 at 10:00:07 UTC, David Nadlinger wrote:
 On Monday, 9 February 2015 at 09:43:26 UTC, Ola Fosheim Grøstad 
 wrote:
 ldc.gccbuiltins_x86.di does not contain:

 __m256 _mm256_add_ps (__m256 a, __m256 b)
 #include "immintrin.h"
 Instruction: vaddps ymm, ymm, ymm
 CPUID Flags: AVX

 But it does contain less important instructions such a 256bit 
 "addsub".

 I am trying to build up a set of standard Intel intrinsics, 
 but not sure how to work around this (or did I miss something?)

 Unfortunately, LLVM only offers intrinsics for operations that 
 are not expressible in standard LLVM IR.

Thanks, I found a "role model" here:

https://llvm.org/svn/llvm-project/cfe/trunk/lib/Headers/avxintrin.h

I guess I will just have to look at that and make my own version.