• Tomek =?UTF-8?B?U293acWEc2tp?= (10/10) Oct 05 2010 I've been reading about caching mechanisms in today's processors -- amaz...
• retard (6/15) Oct 05 2010 What generation of CPUs are you talking about? Based on discussions here...
• bearophile (4/7) Oct 05 2010 I don't know the answer, but regarding cache coherence and immutable dat...
• Don (8/18) Oct 05 2010 Based on my reading of AMD's docs, it should happen automatically.
• #ponce (1/3) Oct 05 2010 Can we expect thread-local storage to be faster than shared memory ?

Tomek =?UTF-8?B?U293acWEc2tp?= <just ask.me> writes:

I've been reading about caching mechanisms in today's processors -- amazing in
their 
intricacy.
It made me wonder, is there a way to exclude immutable regions of memory from a
cache 
coherence mechanism? I mean, let the processor know: no invalidation for cache
lines from 
immutable memory.
And even if it's possible, how much would it really help? I have no intuition
about how 
expensive those coherence mechanisms are.

CPU geeks speak up! :)

-- 
Tomek

retard <re tard.com.invalid> writes:

Tue, 05 Oct 2010 20:49:34 +0200, Tomek Sowiński wrote:

 I've been reading about caching mechanisms in today's processors --
 amazing in their intricacy.
 It made me wonder, is there a way to exclude immutable regions of memory
 from a cache coherence mechanism? I mean, let the processor know: no
 invalidation for cache lines from immutable memory.
 And even if it's possible, how much would it really help? I have no
 intuition about how expensive those coherence mechanisms are.
 
 CPU geeks speak up! :)

What generation of CPUs are you talking about? Based on discussions here, 
it seems people like Nick S. are still using single core, single socket 
PII/PIII class systems. The Opteron/Xeon systems look like NUMA systems 
and consumer systems use the simpler FSB. I don't know about other 
architectures.

bearophile <bearophileHUGS lycos.com> writes:

Tomek S.:

 is there a way to exclude immutable regions of memory from a cache 
 coherence mechanism? I mean, let the processor know: no invalidation for cache
lines from 
 immutable memory.

I don't know the answer, but regarding cache coherence and immutable data, if
your data structure (like a graph) is immutable, then it doesn't need free
spaces and data necessary to allow its growth. So you are often able to pack it
more in memory, and this saves some RAM and reduces cache misses, improving
performance too.

Bye,
bearophile

Don <nospam nospam.com> writes:

Tomek Sowiński wrote:
 I've been reading about caching mechanisms in today's processors -- amazing in
their 
 intricacy.
 It made me wonder, is there a way to exclude immutable regions of memory from
a cache 
 coherence mechanism? I mean, let the processor know: no invalidation for cache
lines from 
 immutable memory.
 And even if it's possible, how much would it really help? I have no intuition
about how 
 expensive those coherence mechanisms are.
 
 CPU geeks speak up! :)
 

Based on my reading of AMD's docs, it should happen automatically.
The cache lines will be marked as 'exclusive' when the first core reads 
them, and will change to 'shared' when other cores read them.
Whenever a new core accesses that memory, it will ALWAYS get it from the 
main memory, never from the other cores.
As far as I know, the cost for cache coherency comes when core-to-core 
transfer is required.

#ponce <spam spam.com> writes:

 As far as I know, the cost for cache coherency comes when core-to-core 
 transfer is required.

Can we expect thread-local storage to be faster than shared memory ?